In order to be able to make memory circuits, logic devices and other semiconductor structures of higher integration density than currently feasible, one has to find ways to further scale down certain components thereof and to improve the accuracy at which such components can be made.
For various reasons, vertical channel transistors are more and more used in highly integrated semiconductor structures, such as DRAMs for example. As shown in FIG. 1, a vertical channel transistor 10 typically has a silicon pillar 11 being perpendicular with respect to the substrate 12 on which it is formed. At the bottom of the pillar 11, which serves as channel, a source 13 is situated. The drain 14 is placed at the opposite end of the pillar 11. The gate electrode 15 is separated from the pillar 11 by a thin gate oxide layer 16. Doped polysilicon 17 is deposited adjacent to the gate electrode 15. As indicated in FIG. 1, the gate polysilicon 17 may be connected to the word line of a memory device, and the drain 14 may be connected to a storage device and the bit line (please note that the storage device is not shown in FIG. 1). The etching of the pillar is of utmost importance.
A conventional plasma etch process is described by Purdes in U.S. Pat. No. 4,521,275. Purdes claims to have achieved vertical etching of silicon using a Cl-containing compound such as BCl.sub.3. The bromine-bearing species used by Purdes cover the newly etched surfaces not subjected to ion bombardment. Since the bromine is relatively heavy, it attacks and errodes the mask. It is another disadvantage of bromine that it is toxic. Purdes applies high pressure and high power to the etch chamber. The process described is predominantly physical and thus mainly suited for the etching of polysilicon. The selectivity of Purdes' process with respect to the mask is rather low. It is further to be noted that in 1983 decoupled plasma etch system were neither known nor available. Experiments have shown that the disclosed process is not suited for etching silicon sidewalls of high aspect ratio (&gt;1). The uniformity which can be achieved using a process as the one proposed by Purdes is in the range of about 6%.
Other authors and inventors propose NF.sub.3 as reactive etchant. This etchant, however, is too aggressive. It attacks almost everything and is non selective. NF.sub.3 is thus not suited for etching vertical sidewalls of high aspect ratio.
In the following, various known etch processes are addressed briefly.
U.S. Pat. No. 5,271,799 concerns the vertical etching of an oxide/metal silicide/polysilicon sandwich structure utilizing two bias levels.
U.S. Pat. No. 5,242,536 relates to an etch process which starts off with a so-called initial breakthrough etch using He/Cl.sub.2 only. Then HBr is added to etch polysilicon anisotropically.
U.S. Pat. No. 5,078,833 concerns an Electron Cyclotron Resonance (ECR) etching device and SiCl.sub.4 /N.sub.2 gas mixed with ClF.sub.3. The end result achieved with this device and choice of reactant species is a trench with a sidewall protecting layer.
U.S. Pat. No. 4,450,042 concerns a plasma etch chemistry comprising chlorine and bromine which allows to etch almost vertical silicon sidewalls. A wide variety of etchant gas species is disclosed as being suitable.
U.S. Pat. No. 5,262,002 relates to the etching of vertical trench profiles by means of multiple Si.sub.3 N.sub.4 layers and multiple etch steps along with some sidewall passivation.
U.S. Pat. No. 5,423,941 concerns a plasma etch chemistry at least comprising Br.
U.S. Pat. No. 5,409,563 relates to a glow discharge system operated at elevated temperatures and being suited for the dry etching of high aspect ratio features in silicon.
U.S. Pat. No. 5,118,383 addresses a method for producing trench structures having smooth sidewalls and straight, flat trench floors by etching in a triode single wafer plate reactor using a gas atmosphere exclusively of chlorine.
In the IBM Technical Disclosure Bulletin, Vol. 27, No. 1B, a lift-off process is described which can be used to form a mask with vertical sidewalls. This mask then may be used to etch narrow trenches using reactive ion etching.
In the article "A Scalable Low Power Vertical Memory", H. I. Hanafi et al., IEDM, Dec. 10-13, 1995, pp. 657-660, floating gate vertical transistors are addressed. The pillars are made using an HCl/Cl.sub.2 /N.sub.2 plasma etch process.
Protruding structures, like pillars, are not only used to form transistors, as shown in FIG. 1, but are also used in connection with various other kinds of devices, such as capacitors, resistors and so forth. For all these applications, it is important that the sidewalls are vertical or nearly vertical and that the sidewall surfaces are even and smooth.
When making vertical FETs, the quality of the sidewall is of particular importance, because an uneven and rough sidewall may cause leakage through the gate oxide and/or the device.
Currently, when etching a silicon substrate to form a protruding structure with vertical or near vertical sidewalls, there are three problems, besides the problem that the sidewall surfaces may not be of sufficient smoothness. Firstly, it is impossible to obtain vertical or near vertical sidewalls of high aspect ratio (heights of vertical sidewall versus width of structure) when using conventional approaches. The sidewalls 20 always are sloped with the angle of slope increasing from about 90.degree. to 80.degree. and less (from top 21 to bottom 22), as schematically illustrated in FIG. 2. Secondly, a foot 23 forms at the bottom of the sidewall 20 and thirdly, a trench 24 appears next to the foot 23, as illustrated in FIG. 2. These effects--known as footing and trenching, respectively--are a function of the chemistry used for etching the protruding structure, the etch time, as well as the micro and macro loading factors. These effects are discussed in the following exemplary articles: "Microtrenching during polysilicon plasma etch", by S. W. Swan et al., Proc. SPIE, Vol. 1803, p. 2-12, 04/1993, and "Profile Control of poly-Si Etching in Electron Cyclotron Resonance Plasma", by N. Rujiwara et al., Jap. J. Appl. Phys, Vol. 34, pp. 2095-2100, Part 1, No. 4B, April 1995.
Trenching, footing and sloped sidewalls are a particular problem in cases where there is no etch-stop layer or a similar means which helps to ensure that the etch step is stopped if the desired etch depth has been reached. Trenching is mainly caused by the focusing of ions along the etched features.
In processes that rely predominantly on the physical mechanisms of sputtering (including RIE), the strongly directional nature of the incident energetic ions allows substrate material to be removed in a highly anisotropic manner, i.e. essentially vertical etch profiles are produced. Unfortunately, such material removal mechanisms are also quite non-selective (also referred to as low selectivity) against both masking material and material underlying the layer being etched. Since in case of the formation of protruding silicon structures on a silicon substrate there is no underlying layer which would serve as etch stop layer, the physical etch process would etch into the substrate thus causing trenching. As a result of these and other drawbacks known to those skilled in the art, etch process based predominantly on the physical removal mechanisms are not suited for the formation of vertical or near vertical sidewalls.
Conventional dry etching processes relying strictly on chemical mechanisms can exhibit very high selectivities against mask materials used. If there is no etch stop layer or the like, as mentioned above, a purely chemical etch step would also etch into the substrate causing trenching and footing. Dry etch processes based on chemical mechanisms typically etch in an isotropic fashion, which is not desired when trying to form vertical or near vertical sidewalls.
When choosing an etch tool and the reactive species for etching a substrate, many factors and parameters have to be taken into consideration:
the etching process should be highly selective against etching the mask; PA1 the etching process should allow to form protruding structures of high aspect ratio; PA1 the etch rate should be rapid, or the throughput of a machine performing the etch should be suitably high; PA1 the etching should be uniform across the entire wafer, from wafer to wafer, and from run to run; PA1 the etch process should cause minimal damage to the substrate or other elements formed in previous steps; PA1 the etch process should be clean (i.e. low incidence of particulate and contamination); PA1 the etch process should be conducive to full automation and batch fabrication; PA1 the etch process should be insensitive to the loading factor, or it should be less sensitive than known processes. PA1 forming a mask on top of a semiconductor substrate defining the lateral size of the protruding structures to be formed in said substrate, PA1 feeding HCl, Cl.sub.2 and N.sub.2 into a plasma chamber to provide an ion plasma when applying source power, and PA1 causing said ions to diffuse towards the substrate by applying a bias power such that the portions of said substrate not being covered by said mask are etched away.
There is no etch process known which meets all the above criteria. There is currently no feasible means to precisely control the etching of protruding silicon structures and to fabricate them such that they have vertical or near vertical sidewalls of high aspect ratio.
It is an object of the present invention to provide a method which allows to make protruding silicon semiconductor structures having a vertical or near vertical sidewall.
It is an object of the present invention to provide a method which allows to make protruding silicon structures without causing footing and/or trenching, or with reduced footing and/or trenching.